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Gallium Arsenide Gate Field-Effect Transistor Process Utilizing Self-Aligned Epitaxial Contacts

IP.com Disclosure Number: IPCOM000058656D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Baratte, H Marks, RF Wright, SL [+details]

Abstract

This article describes a gallium arsenide (GaAs) gate field-effect transistor (FET) process wherein the semiconductor heterostructure simplifies device processing and facilitates regrowth of self-aligned source and drain contacts. Key to the process disclosed herein are differential etch rates of materials which form crystalline, polycrystalline and surface-oxidized layers. Advantage is taken of material selective and spatially selective wet and dry etching means as well as anisotropic (dry) etching. Heteroepitaxy, which is molecular beam epitaxy (MBE), is employed to produce the initial heterostructure grown on GaAs as follows: (a) undoped GaAs buffer layer > 200 nm thick, (b) AlxGal-xAs barrier layer (x = .4-.6) 15-60 nm, (c) n+ GaAs gate 200-400 nm, (d) AlyGa1-yAs (y NN .8) 100-200 nm mask level.