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Isolation Merged Stacked Dynamic Random-Access Memory Cell Disclosure Number: IPCOM000058682D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

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Bronner, GB Dennard, RH Lu, NC [+details]


A technique is described whereby low temperature oxide isolation is added to a stacked dynamic random-access memory (DRAM) cell. Described is a process which produces a DRAM cell structure, using selective epitaxy, to simultaneously overgrow a trench capacitor and to provide an active device area within the structure. (Image Omitted) The process consists of seven major steps: 1) Starting with a p/p+ substrate, a thin oxide is grown thermally followed by deposition of Si3N4 and then SiO2 . The stack produced is patterned by using standard photolithographic techniques to define trench storage areas and is etched using reactive ion etching (RIE). The trenches are etched into the silicon using the stack as a mask.