Very Low Resistance MOS Circuit Wiring
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15
A technique is described to enable the use of device polysilicon gate level in MOS integrated circuits (ICs) as a very low resistance wiring level. This enhances the wireability of logic chips and also results in improved chip performance and density. (Image Omitted) For high-density, high-performance multi-function MOS logic chips, several low resistance wiring levels are required. In fabricating these chips, polysilicon has been used as a device gate material, since it offers several device and process advantages, e.g., self-aligned source/drain regions, possible gate oxidation, etc. Unfortunately, this polysilicon layer may not used for wiring due to its high resistance, typically / 25 L/ . Recently, a technique to reduce the polysilicon layer resistance has been developed. A layer of refractory metal, e.g.