Browse Prior Art Database

56 by 56-Bit High Speed Multiplier

IP.com Disclosure Number: IPCOM000058694D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Desrosiers, B Taroni, G [+details]

Abstract

A high speed multiplier is an indispensable part of a number of applications, such as floating point arithmetic, real time speech processing, image processing, etc. The multiplication of 2 numbers of n bits each is usually done in two steps. The first step consists of adding numbers of n bits to get two 2n-bit partial results. The second step consists of adding these two partial results with an adder. A technique to carry out the first multiplication step was described previously [1] using a Booth algorithm and 7-to-3 counters. The circuits providing the first multiplication step are referred to as the Array Multiply and those in the second step are the Final Adder. The present disclosure provides an original way to get a fast and dense hardware implementation of the Array Multiply.