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Sequence Detect Latch Trigger Disclosure Number: IPCOM000058701D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

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Goodwin, JG [+details]


This invention relates to a clock pulse input and serial data pulse input which trigger a latch pulse from a data latch sequencer for controlling the operation of a shift register. A shift register, such as the one used here, stores serial bits of information for outputting or shifting stored bit units in parallel to a second device utilizing a latch pulse. This sequencer allows a two-input line digital system to utilize a shift register having three input lines (clock pulse, serial data pulse, and latch pulse). These pulses are in a digital waveform consisting of a series of selectively alternating high portions (binary "1" bits) and low portions (binary "0" bits) over a specific time period.