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Redundant System Clocks for Hardware Fault Tolerant Computers Disclosure Number: IPCOM000058712D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue


Related People

Baker, ED Dinwiddie, JM Freeman, BJ Hoffman, SS [+details]


This article describes a circuit arrangement which eliminates a single point of failure exposure in a hardware fault tolerant computer by implementing redundant clocks. Conventionally, hardware fault tolerant computers have a single system clock that is used to synchronize all CPU's memory and I/O controllers. This system clock is a single point of failure that can jeopardize the continuous operation of a fault tolerant computer. On current systems, this single point of failure is minimized by using military specified parts, hooking two crystals in parallel, using dual connectors and making the printed circuit board as small as possible. Unfortunately, if the clock card goes bad, the fault tolerant processor fails.