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Method for Independent Control of Screen Oxide and Edge Spacer Thickness

IP.com Disclosure Number: IPCOM000058713D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Bracchita, JA Cronin, JE [+details]

Abstract

Polysilicon is used to control gate conductor sidewall spacer thickness such that screen oxide thickness is optimized solely for source and drain implantation depth. Thus, device channel length and depth of source and drain doping are independently controlled. Referring to Fig. 1, a gate dielectric 2 is under a gate electrode 4, having width w, on silicon substrate 6. Screen oxide 8 is conformally deposited to a thickness t appropriate for controlling the depth of ion implantation of source 10 and drain 12 dopant. A conformal layer of polysilicon 14, having a thickness d, is then deposited and reactive ion etched (RIE) to add thickness d to the oxide 8 having thickness t on the sidewalls of gate electrode 4. Thus, the ion implantation of dopant in substrate 6 is t+d away from the edges of gate electrode 4.