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High Rate Clock Reconstruction Circuit for Digital Communication

IP.com Disclosure Number: IPCOM000058729D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Balliet, L Bou-Ghannam, A [+details]

Abstract

This article describes a digital clock reconstruction circuit with desirable phase-locked-loop characteristics that can be constructed to operate at rates approaching that of the maximum clock rate for the logic technology being employed. Precision clock reconstruction in digital communication is frequently accomplished by phase-locked-loop circuits, either analog or digital. Analog phase-locked-loops require precision discrete components, are relatively expensive, and without special provisions, do not lock on instantaneously. Furthermore, analog circuits are difficult to integrate with digital logic technology. Conventional digital phase-locked-loops use counters or similar techniques that limit their use to low data rate applications.