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Logical Decoupling of Parallel Error Correction Code Banks With Invert-Retry and Simultaneous Timings

IP.com Disclosure Number: IPCOM000058734D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Arlington, DL Herndon, SB Rogers, JF [+details]

Abstract

Designing a memory card with a single error correct/double error detect (SEC/DED) error correction code (ECC), as well as an invert/retry scheme to correct most double bit errors (DBEs), causes problems when multiple ECC words are closely coupled in timing in order to keep transfer rates high and allow the advantages of duplicated hardware. (Image Omitted) The term "ECC word" refers to a single word protected by an ECC, including its ECC checkbit vector, whether in storage or in a data path. "Closely coupled" means that two or more ECC words will cause invert/retry to occur for all words. The term "bank" is used to describe one complete set of array, ECC and invert retry logic.