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Method for Generating Critical Clock Edges for a Two-Phase Clock System Disclosure Number: IPCOM000058740D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

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Dick, CJ Jones, L Mercier, SJ Roche, TJ Still, GS [+details]


Processor designs typically have generated the actual clock signals of a two-phase clock system early in the system distribution of the critical timing edges. Logic residing on each logic chip can generate these clocks from free-running oscillators to reduce distribution skew, resulting in a simplified distribution scheme. The method works as described in the following. (Image Omitted) In a two-phase clocking scheme, shown for positive active clocks in the timing diagram in Fig. 1, the relative timing of the trailing (falling) edge of the first clock pulse, with respect to the leading (rising) edge of the second clock pulse, determines many of the critical timings in the system. In some applications the leading edge of the first clock pulse is also important.