Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15
A method of debouncing a particular channel-to-channel disable switch is shown in Fig. 1. Two limitations of this particular arrangement are that the latch is not scannable and it also fails timing analysis. A reconfigured circuit, shown in Fig. 2, allows testing and passes timing analysis. The circuit description is as follows. (Image Omitted) When the disable switch is thrown from the SW1 to the SW2 position, SW1 would go to + V and SW2 would bounce before settling to ground level. When SW2 bounced to ground level, point BB would become a logic '1' and this '1' would be clocked into the shift register latch (SRL) by CC. The feedback from Out would make AA a logic '1', thus preventing bounces at BB into the SRL.