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Avoiding SIIS on Processors With Multiple Concurrent Cache Accesses

IP.com Disclosure Number: IPCOM000058754D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Emma, PG Knight, JW Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

A method is provided for detecting the hazard created by storing into an instruction stream (SIIS) in a system utilizing instruction upstreaming. The provided method comprises: comparing the line addresses of fetches to the line addresses of the pending store array; utilizing a mode bit to indicate that upstreaming is permitted; resetting the mode when a close by SIIS is detected; and preventing fetching until after the related STORE has completed where SIIS is detected on a doubleword granularity. One manner of creating a multi-access cache is to initiate requests within the processor that generate multiple cache accesses on successive cycles. The appearance of multiple concurrent accesses is achieved by the overlap of individually issued multi-successive-access requests.