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Improved Generation of N-Ary Logic for Synthesis

IP.com Disclosure Number: IPCOM000058755D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Drum, AD Sweet, CP [+details]

Abstract

An important aspect of logic synthesis is to transform arbitrary collections of AND gates to new sets of AND gates in such a way that they can be physically built on a chip (note that any statement made about AND gates also applies to OR and XOR gates). In any technology, a set of physical gates (which differ in the number of inputs) exist to represent an AND function. For example, a technology may have 2, 3, 4, 8, and 9 input gates available. If a 5-way AND function is to be built in this technology, there are many ways to do it. Two possibilities are shown in Fig. 1 and in Fig. 2. The configuration shown in Fig. 2 has two advantages over the one shown in Fig. 1. First, it takes less space on a chip, and second, signal delays are reduced.