Internal Access Time Measurements for Random-Access Memory Circuits
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15
By means of adding a timing chain to generate an access delay time strobe and compare circuitry on a random-access memory (RAM) chip, the minimum access time of each array cell may be measured, thus avoiding any tester-dependent uncertainties. Referring to the figure, clock signal CLK, from which access time of the chip is measured, is input to chip pad P1 and thence to on-chip receiver (OCR) 2. Output from OCR 2 goes into the inverter timing chain 4, 6, 8 which provides a total path delay through multiplexer (MUX) 10 to latch 12 equal to the minimum access time of the memory under test. By adding additional delay of inverters 14 and 16, a slow timing test is made possible.