Browse Prior Art Database

Logic Chip Performance Customization

IP.com Disclosure Number: IPCOM000058773D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Kleinman, DA [+details]

Abstract

By using an external clock and some circuits and delay lines internal to a chip, performance (speed) of a chip is determined and critical circuit delay paths are optimized. Thus, timing variations created by chip process effects, operating temperature, or clock frequency changes may be compensated automatically. Logic to determine the speed of a chip is shown in Fig. 1. A trigger pulse at IN toggles a signal at set-reset latch (SRL) L2, and a precisely controlled system clock (not shown) for clocking all latches is activated. The signal from latch L2 propogates through incrementally increasing delay lines D1---Dn, wherein delay D1 has a value greater than or equal to a specified set-up requirement of the logic technology.