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Recessed Gate Metal Oxide Silicon Field Effect Transistor Structure

IP.com Disclosure Number: IPCOM000058777D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Parries, PC [+details]

Abstract

Source and drain diffusion separation and gate electrode position are defined with one mask. Since the gate electrode material is deposited after the various high temperature steps (e.g., source/drain diffusion), the gate conductor is selected on bases other than high temperature sensitivity. The diffusion source in this process is a silicide, regionally doped by ion implantation. Thus, diffusions, diffusion contacts, and a level of wiring may be defined at the same time. Referring to the figure, a silicide 2, is blanket deposited on a silicon substrate 4. Blocking masks are used to expose different regions of silicide 2 to ion implantation of dopants of opposite polarity. Implantation energy is selected to contain the dopants entirely within the thickness of silicide 2.