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Dual Work Function Doping

IP.com Disclosure Number: IPCOM000058795D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Harmon, DL Parries, PC Rembetski, JF [+details]

Abstract

A technique is shown for eliminating etch rate differential problems and a masking step when simultaneously etching n and p doped polysilicon when fabricating semiconductors. The conventional approach to dual workfunction electrode fabrication is as follows: 1) Deposit intrinsic polysilicon. 2) Mask and implant n-type dopant. 3) Mask and implant p-type dopant. 4) Optionally add additional layers for gate stack. 5) Mask and pattern entire gate stack. The problem with the conventional approach is that the n-type polysilicon etches 1.4 to 2.0 times faster than p-type polysilicon. Because both types of polysilicon are the same thickness, the n-type areas are opened sooner than the p-type areas. As a result, the underlying gate dielectric is exposed to the etchant for a longer period of time and may be breached.