Method of Debugging Power Management Logic with Existing Scan Chain
Original Publication Date: 2005-Feb-15
Included in the Prior Art Database: 2005-Feb-15
Digital IC designs that support power saving modes involving saving CPU state into off-chip memory and power down the part are easily exposed to logic bugs that can put the chip into a self locking state while the part is still in power down state. Without power to the rest of the chip except the power management unit, which should be kept powered all the time, no existing debug feature can provide the test engineer the access to the internal state of the power management logic. This invention provides a mechanism by which test engineer can access internal state of the power management controller without destroying the controller state of registers.