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Method for Determining Bottom and Array Inputs Disclosure Number: IPCOM000058802D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

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Cox, DT Dewanz, DM [+details]


Many different methods have been described for arriving at a near optimum folding for PLA (programmable logic array). These have suffered from either requiring long computer run times to arrive at a solution, or by making it very difficult to implement a logic change into the PLA without also changing the physical structure. The disclosed method (the folding structure of Figs. 1, 2, and 3 hereof) allows a large degree of freedom to incorporate logic changes while still permitting folding to reduce the PLA area. Most of the problems with previous folding methods are because both AND arrays are folded. The disclosed method frees up bottom product terms by not folding the bottom AND array, the choice of which inputs physical area in the PLA macro (a PLA residing on a single chip).