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Instruction Execution Rate Performance Measurements on a Pipelined Multi-Function Unit Processor

IP.com Disclosure Number: IPCOM000058805D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Rodriguez, JR [+details]

Abstract

This article describes techniques developed to take performance measurements of the internal operations in a pipelined multi-function unit (MFU) processor. An MFU Floating-Point Processor (FPP) is used here as an example. (Image Omitted) The technique described consists of measurements on the execution of individual operations so that it reveals the effect of the program and processor structure on the performance characteristics of a parallel unit. The performance measure used is the instruction execution rate (IER). For a pipelined processor, this can be defined variously as the rate at which the unit accepts instructions for execution at its input, the rate at which it executes instructions, or the rate at which it can provide some results. (Image Omitted) The approach is based on the following two operations: 1.