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High Density Memory Cell Structure With Two Access Transistors

IP.com Disclosure Number: IPCOM000058813D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Dhong, SH Hwang, W Lu, NCC [+details]

Abstract

A technique is described whereby a high density dynamic random access memory (DRAM) cell structure incorporates a pair of access transistors and a capacitor, thereby reducing the structural size of memory cells and improving the immunity to noise. Discussed is the physical layout of the cell, the fabrication process involved, the sense/refresh circuitry and the operational principles. (Image Omitted) Typically, MOS DRAM cells, which contain one access transistor and one storage capacitor, have signal-to-noise ratio and alpha-particle- induced soft error limitations.