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Bit Insertion and Deletion Architecture for Computer-Controlled Data Communications Systems

IP.com Disclosure Number: IPCOM000058840D
Original Publication Date: 1988-Dec-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Davis, GT Mandalia, BD Picon, RJ Russell, R Sinibaldi, J [+details]

Abstract

A technique is described whereby control architecture is incorporated for the handling of multiple channels of SDLC/HDLC or similar protocols in integrated services digital network (ISDN) communications environments, so as to optimize the trade-off between the software overhead of input/output (I/O) processing and added hardware complexity. The architecture allows for sharing of a single hardware circuit, as controlled by the microprocessor, in order to process multiple data links. The architecture is also applicable to non-ISDN environments which involve multiple data links terminated in a single attachment. (Image Omitted) Bit insertion and deletion circuitry has become an integral part of data communications systems due to the requirements of SDLC/HDLC and similar protocols.