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This article relates to the fabrication of a silicon spacer reactant for selective chemical vapor deposition (CVD) of a metal when filling a semiconductor via hole.
English (United States)
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Selective Cvd Via Stud Fabrication Process
This article relates to the fabrication of a silicon spacer reactant for selective
chemical vapor deposition (CVD) of a metal when filling a semiconductor via
Normal methods of forming contact studs for planarized metallurgical
applications in VLSI technology include reactive ion etch-back of deposited metal
or a metal lift-off process. Negating factors for the reactive ion etch-back process
include process complexity, uniformity control problems and damage to the
adhesion layer by the vertical etch. When the lift-off process is used, complicated
photo resist processes and the inherent negative sidewall slope of the metal stud
can be a source of reliability problems.
By physically depositing a polysilicon or amorphous silicon via hole sidewall
nucleation structure, the selective deposition of a metal within the contact hole is
enhanced. Shown in the figure is a via hole which has been exposed to a blanket
deposition of silicon (a) followed by a reactive ion etch (RIE) of the silicon to
leave a spacer of deposited silicon on the via hole sidewall (b). The spacer
provides a large nucleation surface on the sidewall in addition to the silicon or
metal surface at the bottom of the hole. A lateral selective deposition of metal (c)
is used to fill the contact hole.
This simplified contact stud fabrication process provides a positive sloped
spacer surface after the RIE step which enables the hole to be filled easily by