Browse Prior Art Database

Logical Implementation of the Set And Reset Features in Level Sense Scan Latch Circuit Designs

IP.com Disclosure Number: IPCOM000058929D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Staddon, DR, Jr [+details]

Abstract

A technique is disclosed for capturing an asynchronous signal (SET) with either immediate or delayed detection and then clearing that signal (RESET) with either greater or less priority than the set condition.