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A high density random access memory (RAM) cell is shown which can be tested utilizing level sense scan design (LSSD) techniques.
English (United States)
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A High Density Random Access Memory Cell Adapted to Level Sense Scan
Design Test Methods
A high density random access memory (RAM) cell is shown which can be
tested utilizing level sense scan design (LSSD) techniques.
RAM cells designed in a conventional manner cannot be read or written using
LSSD stuck fault testing methods. As a result, severe test penalties are paid by
systems that use imbedded RAMS. To effectively test these RAMS, access to
input/output (I/O) lines and cell control logic is gained through chip I/O pins.
Valuable chip I/O pins and test time can be saved by modifying imbedded RAM
designs so that these RAMs may be included in LSSD stuck fault tests.
By adding a pass device to each RAM cell as shown in Fig. 1, data can be
propagated from cell to cell as the memory is clocked alternately with non-
overlapping "A" & "B" clock pulses. This technique establishes a serial scan
string for the entire array. Also, a scannable RAM can be preset to any desired
state in the test mode by using the scan string. This may eliminate initial
diagnostic testing done to check for a RAM's functionality. Note that every other
bit line BL, i.e., BL true BLT and BL complement BLC, is swapped when passing
data to be scanned out.
Fig. 2 shows a functional block diagram of the interconnect system used for
clocking a scannable RAM design during a LSSD test procedure. It should be
noted that this design technique for adapting RAMS to LSSD test methods is also