Processor Segment Register Lock Bit
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15
This article describes a technique for use in a processor which provides for the addition of a segment register "lock bit" that gives the supervisor or other privileged program the mechanism to prevent a non-privileged program from using a non-privileged segment register load (NPSRL) instruction to alter the contents of a segment register which is being used by another program within the same address space. When permitted by the lock mechanism, the NPSRL instruction may be issued by a non-privileged program to load the contents of a segment register from a table maintained by the privileged supervisor in protected storage.