Browse Prior Art Database

ROM Activated Zero Wait States for Computer Memory Address Ranges

IP.com Disclosure Number: IPCOM000059019D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Aldereguia, A Price, WE [+details]

Abstract

A technique is described whereby a read only memory (ROM) circuit module provides the output necessary for computer memory circuitry to enter zero wait state operations. The concept enables computer system memory boards to be increased and to perform at zero wait states, without modifying the basic circuit board. It also allows the computer system to run in default wait states, in the event main memory devices are too slow for the operation.