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Concept Search - What can I type?
For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.
Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.
A method is shown for incorporating a capacitor in a small outline "J" (SOJ)
plastic semiconductor package for the purpose of minimizing on chip voltage
collapse and reducing electrical ground noise.
Testing a SOJ package in a noise-free manner is difficult due to the frailty of
the package leads and is complicated by large current surges resulting in
electrical ground movement called "ground bounce". This problem is experienced
with dynamic and static random access memories and logic chips as well. The
classic problem resulting from "ground bounce" is to artificially diminish the most
positive down level (MPDL) and the least positive up level (LPUL) input margins.
In most semiconductor designs, voltage applied to a chip's input receivers is
referenced to card ground. Voltage excursions at chip ground causes the
receiver input voltage to appear higher or lower by the delta difference between
card and chip ground. Since only several hundred millivolts of margin typically
exist to correctly distinguish between a high and a low input level, small voltage
excursions at chip ground can cause a incorrect address or a invalid control
signal to be sensed during testing and results in a yield loss.
By integrating a discrete capacitor into a plastic SOJ package and connecting
it directly across the voltage (Vdd) and ground (Gnd) package leads by solder or
conductive epoxy (no wire bonds), as shown in the figure, the ch...