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The following design rule checking algorithm checks the external latchup rules. This is the first checking algorithm of its kind in the semiconductor industry.
English (United States)
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External Latchup Design Rule Checking
The figures below describe the design rule checking algorithm to find potential areas
where external latchup1 could happen. Latchup causes a low-resistive path between
VDD and GND, which can lead to chip destruction. There are two classes of latchup:
internal and external. There are two subclasses of external latchup. The first is caused
by either off-chip signals received by I/O circuits which generate enough voltage bounce
or carrier injection to trigger latchup in the I/O itself. The second occurs when these
carriers are not contained in the I/O then latchup occurs in the weakest internal circuits
adjacent to the I/O cells.
Figure 1: Overall algorithm
(1) Ground Rules:
Ex: (P+ junction < y from INJECTOR shape)
maximum distance ≥ z to n-well contact
Ex: (N+ junction < y from INJECTOR shape)
maximum distance ≥ z to substrate contact
(2) Applies only to:
N-junctions near (n-wells enclosing
P-junctions in (n-wells near n-junctions)
(3) Where z is the ground rule value, y is
distance from junction to INJECTOR from
ground rule description, and increment value is
(minimum n-well width / √2) for n-junction or
(minimum n-well space / √2) for p-junction:
NOTE: Increment value is chosen to be as
large as possible to minimize iterations, but not
so large as to "jump" over NW shapes (in the
case of n-junction expands) or "jump" to the
next NW shapes (in the case of p-junction