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A method is described for allowing use of different instruction store access timings in a high-speed micro-computer system.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
76% of the total text.
Page 1 of 1
Method And Apparatus to Allow Use of Different Timings for Accessing
Instruction Store in a High-Speed Micro-Controller
A method is described for allowing use of different instruction store access
timings in a high-speed micro-computer system.
In a high-speed, non-pipelined, micro-controller multi-clock system, internal
clock phases are used to control instruction execution and address generation.
The generation of the next instruction address is normally dedicated to a
particular phase within the instruction cycle time. This phase is usually fixed
while the selection of the clock phase is determined by the execution unit. With
different clock oscillator speeds, the system can run with different clock cycles. If
the clock phase for generating an instruction address is fixed, a phase must be
chosen which would satisfy the worst case application where the cycle time is at
As an example, consider a system which has a cycle time of 160 ns
comprising of 8 equal clock phases with phase 5 being chosen for generating an
instruction address. Suppose a cycle time of 300 ns with 8 equal clock phases is
needed. Since phase 5 is chosen for generating the instruction address, the
access time allowed for the instruction store memory is 112.5 ns. As the
instruction execution time is fixed, it is possible to use phase 4 to generate the
instruction address so that instruction store memory with a maximum access time
of 150 ns can be used. But because of the traditional...