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A method for utilizing third level metal M3 pad transfer technology to provide an easily probable grid for bench analysis of large, high pin count semiconductor chips is shown.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
75% of the total text.
Page 1 of 1
Third Level Metal Diagnostic Image
A method for utilizing third level metal M3 pad transfer technology to provide
an easily probable grid for bench analysis of large, high pin count semiconductor
chips is shown.
When bench analysis is required to locate specific failure causes, usually on
a new chip design, a probe card which accommodates a large number of probes
for contacting chip pads is needed. By relaxing the ground rules used in the initial
chip design, a high pin count probe card may be produced specifically for the
bench testing required to isolate design or mask induced errors. This disclosure
only applies to processed wafers which have not reached the post-lead-tin (PLT)
One way to achieve relaxed ground rules for custom probe cards is to utilize
third level (M3) technology to transfer the pads of selected chips outward, over
kerf and over adjacent chips as shown in the figure. To implement this scheme, a
set of custom masks is designed for each new chip design. The custom 1x mask
set includes one M3 level mask, one terminal via (TV) mask and one edge seal
(ES) mask. The set extends the chip pads from the second level metal (M2)
outward from the chip into the kerf area and adjacent chip area to an array of
large, easily probable M3 pads. By using two rows of pads/side arranged in
either single or double rows, a standard probe card with adequate capacity may
be fabricated. The M3 line is made as wide as possible after the ES contact to