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Conditional Endop

IP.com Disclosure Number: IPCOM000059509D
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-16

Publishing Venue

IBM

Related People

Authors:
Frye, HE Funk, MR Petz, BR [+details]

Abstract

Described is a mechanism by which processing of a next instruction by of CPU can conditionally begin based upon various parameters. 1) Advancement of the Instruction Address Register (IAR) 2) Setting of the Internal Microprogram Interface (IMPL) Condition Code Register (CC) 3) Interpretation of the next IMPI instruction Opcode and Trapping to the HMC routine supporting the next IMPI instruction 4) Loading of the Instruction Length Register (IL) 5) Loading of the Operand length register (L) 6) Pre-accessing of the base register offset