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For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.
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A technique is described whereby the performance of cache memory is improved by reducing the cache miss penalty by serving the cache miss as two mini-misses that are processed in parallel.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
74% of the total text.
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Improving Operational Performance of Cache Memories - by Reducing
Cache Miss Penalties
A technique is described whereby the performance of cache memory is
improved by reducing the cache miss penalty by serving the cache miss as two
mini-misses that are processed in parallel.
The most critical aspect of the cache miss trailing edge is its duration. In
certain memory hierarchies, limitations on bandwidth can be overcome by
serving the cache miss as two mini-misses that are processed in parallel. The
particular memory hierarchy that allows for such an improvement involves a
Level 1 (L1) cache that is connected to two storage control elements (SCE's).
The purpose of connecting the processor to multiple SCE's might be to reduce
the overall store traffic within a multiprocessor configuration if the L1 levels are
write-through (WT). The limitation on pins from the SCE to all processors
connected to it may force the bandwidth to be a mere doubleword (DW) per
cycle, while the bandwidth to the cache arrays can be a quadword (QW) per
cycle. Such a cache structure affords the designer an alternate line putaway
strategy with intervening cycles as opportunities for cache accesses by the
The concept uses the aggregate bandwidth of both SCE's to transfer data
concurrently for the upper and lower half of the cache line. Therefore, each SCE
is transferring a half line at a DW rate, which is being put away in the cache
arrays at a QW rate. The resultant action achieves a...