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Processor Control Using Cycle Types

IP.com Disclosure Number: IPCOM000059608D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Finney, DW [+details]

Abstract

This article describes a processor control technique utilizing cycle types to keep all subunits of the CPU synchronized. In a pipelined processor with total hardware control, the processor logic can be partitioned in several chips by functions so that each chip requires different control lines to be generated, as illustrated in block diagram in Fig. 1 which shows the processor and storage management unit. In order to minimize the amount of wiring between chips and the number of drivers and receivers required, which causes excessive logic delays and degrades overall processor performance, the next instruction is loaded into a set of control registers in each chip. These control registers are illustrated in Fig. 2 for the control chip.