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Multi-Write/Single-Read Memory Access Scheme for Common Data Base Multiprocessor System

IP.com Disclosure Number: IPCOM000059611D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Chang, LL Dorak, JJ Dunn, JM Rettew, JH [+details]

Abstract

This article describes a multi-write/single-read (MWSR) memory access technique for a common data base multiprocessor system which increases the accessibility of the common data base. In a conventional common data base multiprocessor system, the address and data buses connected to the common data base are controlled by a bus arbiter so that the bus contention problem can be avoided. This method of avoiding bus contention reduces the accessibility of the data base a great deal. If more than one processor needs to access the data base, only one of them will be granted the control. All the rest have to wait until the selected processor finishes its operation. The MWSR memory access scheme disclosed herein is devised to increase the efficiency of the common data base accessibility in a multiprocessor system.