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Dual-Port Queue for Dual-Processor Systems Disclosure Number: IPCOM000059613D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

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Chang, LL Dorak, JJ Dunn, JM Rettew, JH [+details]


This article describes an arrangement for increasing the usability of the communication area in a dual-processor system without causing any bus arbitration problem. In a conventional dual-processor system, the communication area for information exchange between two processors usually causes bus contention problems. The mostly-used method to avoid this problem is using a bus arbiter to control the access of this communication area. The basic bus arbitration principle is that only one processor is allowed to access this area at any time. If more processors than one need to access this area, only one of them is to be granted the control; the other one has to wait until the selected processor finishes its task. Processor's processing time is wasted during the waiting period.