Browse Prior Art Database

Three-Dimensional Organization of I2L Memory Cells

IP.com Disclosure Number: IPCOM000059641D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

I2L (Integrated-Injection Logic) memory cells are generally arranged in two-dimensional arrays containing a designated number of word lines and bit lines. A three-dimensional arrangement of memory cells is described in this article which offers reduced cycle time, simplified support circuits, and provision for ready array expansion when necessary. Memory array performance, in general, is influenced by the number of word lines and bit lines involved in its organization. In some I2L arrays, the array functionality and cell stability are also sensitive to the number of word lines and bit lines used. In the memory organization shown in Figs. 1 and 2, the number of word lines is designated by #W and the number of bit lines by #B. The bit pairs are divided into several bit groups whose number is designated as #BG.