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Branch Bit Testing Using Rotate, Mask Generate and Merge Operations

IP.com Disclosure Number: IPCOM000059647D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Awsienko, O Blake, SP Nahata, P [+details]

Abstract

A technique is described whereby computer architecture, which must have the ability to perform branch bit testing, is executed through the use of rotate, mask and merge instructions. The branch bit testing is performed by implementing an algorithm which utilizes existing functions within the system, required for other applications. Typically, a conditional branch command in computer architecture consists of instructions, e.g., Branch True (BT), Branch True with Execute (BTX), Branch False (BF), Branch False with Execute (BFX), etc., which perform a conditional branch based on the state of a bit selected from a particular register. The bit position and the register to be tested are specified with immediate fields in the instruction code.