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Input/Output Bus Throughput Enhancer

IP.com Disclosure Number: IPCOM000059649D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Awsienko, O Billingsley, RE Nahata, P [+details]

Abstract

A technique is described whereby the input/output (I/O) communications bus control circuitry in microprocessor systems is enhanced so as to obtain a 20 percent increase in throughput. The I/O bus is used in microprocessor systems to provide a communications media to external devices, such as printers, memory files, etc. When one device is required to communicate to another device, control is obtained so as to send a select cycle followed by data cycles, as required. Under prior art, the processor would send the origin address to the selected device at every data cycle. This causes a slow-down of the I/O bus performance. The concept presented herein provides for the transmission of read data cycles only during the first data cycle instead of every data cycle, thereby enhancing I/O bus performance.