Resistive-Coupled, Bipolar, Static RAM Cell
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
An improved, integrated semiconductor circuit bipolar random-access memory (RAM) cell is described where each half of the cell employs a transistor with an intrinsic base resistor to act as the load. The geometric arrangement in the semiconductor is used to connect this load to the active transistor of the half cell. This is in contrast with the normal approach where a separate resistor region is used as the load. Fig. 1 shows a typical circuit employing the new configuration. The circuit is similar to those commonly used as a RAM cell. Node 34 would normally be a bit line connection of a memory array, with node 35 being the complementary bit line connection. Transistor 2 is the output device for node 34.