Browse Prior Art Database

Fault-Masking Memory Array Redundancy

IP.com Disclosure Number: IPCOM000059656D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Robortaccio, R Wang, WY [+details]

Abstract

Fault-masking array redundancy is a system which uses duplicate arrays of memory cells, each with their peripheral drive and selection circuits, in conjunction with a special dual-differential sense amplifier to provide dynamic single-error correction. The data is duplicated in each of the two independent memory arrays, and correct data is read out if the data in at least one of the two arrays is correct. The correct data is selected providing that the defective cell high voltage error level is lower than the normal cell high level voltage. The single-cell failure modes meeting such criterion include 1) collector-to-emitter parasitic path, 2) base-to- emitter parasitic path, or 3) resistor open. The same technique also corrects errors due to shorts or opens in bit or word lines.