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Fault Model of a Non-Scannable Latch Circuit

IP.com Disclosure Number: IPCOM000059658D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Wu, DM [+details]

Abstract

In a general-purpose register, a typical latch circuit used is very difficult to test for all DC defects. A new model logic representation for fault testing the latch circuit is described which will detect all common DC defects. Fig. 1 is a schematic diagram of a latch circuit which is part of a general-purpose register. The key elements of interest are transistors 1 through 6 and the ports 7 through 15. Fig. 2 shows a logic diagram for fault-detection purposes which is equivalent functionally to the circuit of Fig. 1. The ports are numbered the same and correspond to those in Fig. 1. Although Fig. 2 represents the logic of Fig. 1 when all elements are working properly, it cannot be used to detect all single common faults which may be present in the circuit. Specifically, the Fig. 2 diagram cannot be used to detect: 1.