High Performance Single-Ended Multiport CMOS Memory Cell
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
A high density and high performance multi-port memory cell made possible by the use of a pseudo sense line in place of a full dual-ended sense line is described. The storage cell and sensing circuit shown in Fig. 1 use single- bit lines Out 1 and Out 2 for each signal. The signal is generated from the comparison of two voltage levels made possible by the inclusion of Sense Line which simulates a bit line pair. By using device TL to precisely match the loading seen on Out 1 and Out 2 lines, a voltage difference between the Out line and Sense line at the time the Set signal is fired determines the amount of signal available across the Sense Amplifier (SA). The polarity of this voltage determines the contents of the cell.