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Implementation of IBM System 370 Via Co-Microprocessors Exception Handling

IP.com Disclosure Number: IPCOM000059677D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Buonomo, JP Houghtalen, SR Losinger, RE Oliver, BL Valashinas, JW [+details]

Abstract

The implementation of IBM System 370 (S/370) architecture through the use of co-microprocessors was realized on the Personal Computer (PC) XT/370. One of the problems encountered in a system utilizing co- processors is developing an efficient method of handling exception conditions as they can occur on any of the processors and at any time. In the case of the PC XT/370, two Motorola 68000-like processors share the processor load; one being the master, and the other being the slave. The master processor is internally microcoded to interpret 72 of the most frequently used 370 instructions. If the master should encounter an instruction that it does not have in its repertoire, it passes a parameter list through a common storage interface to the slave processor.