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Via Sidewall Shaping by Projection Image Degradation

IP.com Disclosure Number: IPCOM000059680D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bradley, AR Lauffer, JM Nelson, TC Nicholson, JM [+details]

Abstract

In the fabrication of semiconductor integrated circuits having multi- level metallization, it is important to control the sidewall slope of the vias in the insulating layers that provide contact points between metal layers. The disclosed process utilizes a mask pellicle to degrade the projected image and achieve an improved via sidewall slope. A via having too steep a slope or sharp edges can result in step- coverage defects in the overlying metal layer. Conventional methods for controlling the sidewall slope include modifying the chemical constituents of the photoresist used to define the via or altering the etching parameters during via formation. Alternatively, a post-develop heating step may be used to reflow the photoresist and produce a degraded mask image which is transferred to the insulating layer during etching.