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Reliability and Serviceability Enhancement for Multi-Bit Array Chip Storage

IP.com Disclosure Number: IPCOM000059684D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Ruane, AJ Zurla, FA [+details]

Abstract

Multi-bit errors that are caused by a chip kill create an uncorrectable error situation. A redundant bit implementation can be used to replace bad bits on a chip for chip basis in storage designs that have an array with more that one bit per chip in an error checking and correcting (ECC) word. However, redundant bit implementation causes system degradation by placing additional delay in the ECC path due to packet correction circuitry. In situations where array failure caused by chip kills is significant, redundant bit implementation will cause substantial system degradation.