Browse Prior Art Database

Dynamic Error Checking and Correcting ON/OFF Mechanism

IP.com Disclosure Number: IPCOM000059697D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Boguski, MJ Callahan, RW Houghtalen, SR Hughes, JE Kodukula, S Preston, DC [+details]

Abstract

There are systems that allow error checking and correcting (ECC) logic enable or disable for diagnostic function. However, in a normal operating environment toggling from one mode to the other would cause double-bit errors, due to improper initialization of the check bits. To overcome this problem, the whole memory must be initialized with ECC enabled before any read cycles are performed by the system. A method of selecting or bypassing ECC dynamically, without the need to initialize the memory, is described in the following. Microprocessors, such as a Motorola 68000, require an input response to a memory bus cycle to terminate normally (i.e., valid data available at the processor bus on a read cycle or data accepted by the memory on a write cycle) or abort the cycle in case of any exception conditions.