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High Speed Depletion-Mode Read-Only Storage Array

IP.com Disclosure Number: IPCOM000059701D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Kalter, HL Wiedman, FW [+details]

Abstract

This MOSFET read-only storage (ROS) array uses NOR logic and provides access times approaching those of bipolar circuits when word and bit access lines are fabricated with metal conductors rather than with polysilicon or diffusions. Fig. 1 shows a group of four memory cells in a depletion-mode NOR ROS array. Each memory device is coupled to three signal lines crossing the memory array. A word line WL provides an accessing signal to a selected column of memory devices while a bit line BL and a return line R are used to determine whether a particular device has had its channel region ion implanted to convert it from a normal enhancement mode device to a depletion-mode device. Memory devices T11 and T22 are shown as depletion-mode devices. Fig. 2 shows the pulse program for the signal voltages used in the array of Fig. 1.