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Selective Deposition of Studs to Interconnect Metallization Layers Separated by an Insulator

IP.com Disclosure Number: IPCOM000059718D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bertelsen, B Cronin, J [+details]

Abstract

A self-aligned three-dimensional wiring process is described which improves the contact resistance, results in a higher conductive line pitch and significantly simplifies the process of via stud formation. After a via is created in an insulator, the via is partially filled by a selective deposition of tungsten. A layer of aluminum (Al) is then selectively deposited in the via on top of the tungsten (W). A layer of tungsten or molybdenum (Mo) is then selectively deposited over the aluminum layer. Layers of titanium (Ti) and aluminum are then non- selectively deposited over the entire surface and are etched using conventional reactive ion etch (RIE) techniques. The "selective" depositions of the above metals are accomplished by adjusting the chemical vapor deposition (CVD) parameters, such as gas type, pressure and temperature.