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Metal Oxide Silicon Integrated Circuit Substrate Bias Circuit

IP.com Disclosure Number: IPCOM000059726D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bednar, TR Cecchi, DR Kueper, TW [+details]

Abstract

Prevention of minority carriers (usually electrons) from being injected into the substrate is featured in this metal oxide silicon (MOS) substrate bias circuit. MOS on-chip substrate voltage generators have the following basic elements, as shown in the figure: 1) A ring oscillator to generate AC signals from a power supply. 2) A coupling capacitor "CC" to remove any DC offset voltage. 3) A rectifier 10 to convert the AC signal to a negative volt age. 4) An optional regulator (not shown) to control the magnitude of the voltage generated. The ring oscillator signal A is coupled through coupling capacitor CC to drive the field-effect transistor (FET) 10. Negative excursions of the drive pulse E cause transistor 10 to cut-off and rectify the square-wave pulses which bias the drain of transistor 11.